MCU Clock Tree Calculator
Simulate generic PLL, prescalers, and bus frequency distributions. Visualize the clock path from oscillator to peripherals.
Source Frequency
MHz
OR
MHz
MUX
PLL Input
16 MHz
PLL Configuration
×
/
SYSCLK (System Core)
168 MHz
AHB Prescaler (HCLK)
Bus Clock:
168 MHz
APB1 Prescaler (Low Speed)
PCLK1:
42 MHz
Timer (x2):
84
MHz
APB2 Prescaler (High Speed)
PCLK2:
84 MHz
Timer (x2):
168
MHz
Timer Logic: If APB Prescaler = 1, Timer Clock = Bus Clock. Otherwise, Timer Clock
=
Bus Clock × 2.
Validations: Generic checks for division-by-zero or negative values. Check your specific datasheet for max frequency limits (e.g. 168MHz vs 84MHz).
Validations: Generic checks for division-by-zero or negative values. Check your specific datasheet for max frequency limits (e.g. 168MHz vs 84MHz).